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ICCAD
2000
IEEE
109views Hardware» more  ICCAD 2000»
15 years 2 months ago
Latency-Guided On-Chip Bus Network Design
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
Milenko Drinic, Darko Kirovski, Seapahn Meguerdich...
ICNP
2000
IEEE
15 years 2 months ago
General AIMD Congestion Control
Instead of the increase-by-onedecrease-to-halfstrategy used in TCP Reno for congestion window adjustment, we consider the general case such that the increase value and decrease ra...
Yang Richard Yang, Simon S. Lam
ISPD
2000
ACM
131views Hardware» more  ISPD 2000»
15 years 2 months ago
Multi-center congestion estimation and minimization during placement
As technology advances, more and more issues need to be considered in the placement stage, e.g., wirelength, congestion, timing, coupling. It is very hard to consider all of them ...
Maogang Wang, Xiaojian Yang, Kenneth Eguro, Majid ...
ECAI
2000
Springer
15 years 2 months ago
Autosteve: Automated Electrical Design Analysis
AutoSteve performs automated electrical design based on qualitative simulation and functional abstraction. It is the first commercial product capable of performing these tasks for ...
Chris Price
SSDBM
2010
IEEE
220views Database» more  SSDBM 2010»
15 years 2 months ago
Prefix Tree Indexing for Similarity Search and Similarity Joins on Genomic Data
Similarity search and similarity join on strings are important for applications such as duplicate detection, error detection, data cleansing, or comparison of biological sequences....
Astrid Rheinländer, Martin Knobloch, Nicky Ho...