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» High-level area and power estimation for VLSI circuits
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GLVLSI
2006
IEEE
193views VLSI» more  GLVLSI 2006»
15 years 3 months ago
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
GLVLSI
2005
IEEE
104views VLSI» more  GLVLSI 2005»
15 years 3 months ago
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
Ajay Joshi, Jeffrey A. Davis
VLSID
2001
IEEE
132views VLSI» more  VLSID 2001»
15 years 10 months ago
Accurate Power Macro-modeling Techniques for Complex RTL Circuits
This paper presents novel techniques for the cycle-accurate power macro-modeling of complex RTL components. The proposed techniques are based on the observation that RTL component...
Nachiketh R. Potlapally, Michael S. Hsiao, Anand R...
FCCM
2006
IEEE
162views VLSI» more  FCCM 2006»
15 years 3 months ago
Power Visualization, Analysis, and Optimization Tools for FPGAs
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools lever...
Matthew French, Li Wang, Michael J. Wirthlin
VLSID
1999
IEEE
139views VLSI» more  VLSID 1999»
15 years 1 months ago
Processor Modeling for Hardware Software Codesign
In hardware - software codesign paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific...
V. Rajesh, Rajat Moona