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» High-level area and power estimation for VLSI circuits
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GLVLSI
2005
IEEE
144views VLSI» more  GLVLSI 2005»
15 years 3 months ago
On-chip power distribution grids with multiple supply voltages for high performance integrated circuits
—On-chip power distribution grids with multiple supply voltages are discussed in this paper. Two types of interdigitated and paired power distribution grids with multiple supply ...
Mikhail Popovich, Eby G. Friedman, Michael Sotman,...
DAC
1998
ACM
15 years 10 months ago
Maximum Power Estimation Using the Limiting Distributions of Extreme Order Statistics
In this paper we present a statistical method for estimating the maximum power consumption in VLSI circuits. The method is based on the theory of extreme order statistics applied ...
Qinru Qiu, Qing Wu, Massoud Pedram
81
Voted
DAC
2002
ACM
15 years 10 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...
GLVLSI
2009
IEEE
262views VLSI» more  GLVLSI 2009»
14 years 7 months ago
Power distribution paths in 3-D ICS
Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (...
Vasilis F. Pavlidis, Giovanni De Micheli
DFT
2002
IEEE
103views VLSI» more  DFT 2002»
15 years 2 months ago
Input Ordering in Concurrent Checkers to Reduce Power Consumption
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
Kartik Mohanram, Nur A. Touba