181 search results - page 20 / 37 » High-level area and power estimation for VLSI circuits |
GLVLSI
2007
IEEE
15 years 1 months ago
2007
IEEE
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
66
Voted
DAC
2007
ACM
15 years 10 months ago
2007
ACM
We present an efficient technique for finding the mean and variance of the full-chip leakage of a candidate design, while considering logic-structures and both die-to-die and with...
GLVLSI
2000
IEEE
15 years 2 months ago
2000
IEEE
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...
GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
ISVLSI
2008
IEEE
15 years 4 months ago
2008
IEEE
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and ban...