181 search results - page 21 / 37 » High-level area and power estimation for VLSI circuits |
GLVLSI
2007
IEEE
14 years 11 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
71
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ICCAD
2007
IEEE
15 years 6 months ago
2007
IEEE
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
127
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ISPD
2012
ACM
13 years 5 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
Traditional RTL power optimization techniques commit transformations at the RTL based on the estimation of area, delay and power. However, because of inadequate power and delay in...
DATE
1998
IEEE
15 years 1 months ago
1998
IEEE
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...