181 search results - page 24 / 37 » High-level area and power estimation for VLSI circuits |
CODES
2008
IEEE
14 years 9 months ago
2008
IEEE
With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...
104
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ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
ICCAD
2008
IEEE
15 years 4 months ago
2008
IEEE
— Dynamic power noises may not only degrade the circuit performance but also reduce the noise margin which may result in the functional errors in integrated circuit. Decoupling c...
183
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GLVLSI
2011
IEEE
14 years 1 months ago
2011
IEEE
Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subt...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
VLSI timing analysis and power estimation target the same circuit switching activity. Power estimation techniques are categorized as (1) static, (2) statistical, and (3) simulatio...