181 search results - page 30 / 37 » High-level area and power estimation for VLSI circuits |
78
Voted
VLSID
1997
IEEE
15 years 1 months ago
1997
IEEE
Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptiblity of the bias lines to noise...
105
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CODES
2003
IEEE
15 years 2 months ago
2003
IEEE
In this paper, we describe a new methodology based on game theory for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of schedulin...
DFT
2005
IEEE
15 years 3 months ago
2005
IEEE
Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
78
Voted
GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
DATE
1999
IEEE
15 years 1 months ago
1999
IEEE
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...