181 search results - page 31 / 37 » High-level area and power estimation for VLSI circuits |
GLVLSI
2010
IEEE
14 years 9 months ago
2010
IEEE
We revisit voltage partitioning problem when the mapped voltages of functional units are predetermined. If energy consumption is estimated by formulation E = CV 2 , a published wo...
TVLSI
2008
14 years 9 months ago
2008
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
94
Voted
DAC
2004
ACM
15 years 10 months ago
2004
ACM
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...
62
Voted
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
— Increasingly prominent variational effects impose imminent threat to the progress of VLSI technology. This work explores redundancy, which is a well-known fault tolerance techn...
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progress...