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» High-level area and power estimation for VLSI circuits
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AFRICACRYPT
2010
Springer
15 years 4 months ago
Fresh Re-keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices
The market for RFID technology has grown rapidly over the past few years. Going along with the proliferation of RFID technology is an increasing demand for secure and privacy-prese...
Marcel Medwed, François-Xavier Standaert, J...
ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
15 years 1 months ago
Repeater insertion in RLC lines for minimum propagation delay
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
Yehea I. Ismail, Eby G. Friedman
DAC
2005
ACM
14 years 11 months ago
Partitioning-based approach to fast on-chip decap budgeting and minimization
This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today’s ...
Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, ...
SBCCI
2006
ACM
139views VLSI» more  SBCCI 2006»
15 years 3 months ago
Infrastructure for dynamic reconfigurable systems: choices and trade-offs
Platform-based design is a method to implement complex SoCs, avoiding chip design from scratch. A promising evolution of platform-based design are MPSoC. Such generic architecture...
Leandro Möller, Rafael Soares, Ewerson Carval...
FCCM
1999
IEEE
134views VLSI» more  FCCM 1999»
15 years 1 months ago
Runlength Compression Techniques for FPGA Configurations
The time it takes to reconfigure FPGAs can be a significant overhead for reconfigurable computing. In this paper we develop new compression algorithms for FPGA configurations that...
Scott Hauck, William D. Wilson