181 search results - page 5 / 37 » High-level area and power estimation for VLSI circuits |
ISLPED
1996
ACM
15 years 1 months ago
1996
ACM
In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. Present statistical techniques estimate the average power ba...
DFT
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find scaling factor of the IC design whi...
105
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CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
110
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VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
ICCAD
2000
IEEE
15 years 2 months ago
2000
IEEE
In this paper, we present simulation techniques to estimate the worst-case voltage variation using a RC model for the power distribution network. Pattern independent maximum envel...