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» High-level area and power estimation for VLSI circuits
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GLVLSI
2010
IEEE
234views VLSI» more  GLVLSI 2010»
15 years 2 months ago
On-chip point-of-load voltage regulator for distributed power supplies
An ultra-low area, current efficient voltage regulator appropriate for distributed point-of-load voltage regulation in high performance integrated circuits (ICs) is described in t...
Selcuk Kose, Eby G. Friedman
ASPDAC
2004
ACM
126views Hardware» more  ASPDAC 2004»
15 years 3 months ago
High-level area and power-up current estimation considering rich cell library
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel,...
VLSID
2002
IEEE
107views VLSI» more  VLSID 2002»
15 years 10 months ago
Estimation of Maximum Power-Up Current
Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-...
Fei Li, Lei He, Kewal K. Saluja
EAAI
2006
189views more  EAAI 2006»
14 years 9 months ago
Evolutionary algorithms for VLSI multi-objective netlist partitioning
The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partition especially in VLSI ...
Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Aba...
GLVLSI
2007
IEEE
111views VLSI» more  GLVLSI 2007»
15 years 3 months ago
Probabilistic gate-level power estimation using a novel waveform set method
A probabilistic power estimation technique for combinational circuits is presented. A novel set of simple waveforms is the kernel of this technique. The transition density of each...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Ein...