140 search results - page 14 / 28 » High-level design for asynchronous logic |
101
Voted
EURODAC
1994
IEEE
15 years 6 months ago
1994
IEEE
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...
113
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ARVLSI
1997
IEEE
15 years 6 months ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
115
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DAC
2007
ACM
16 years 2 months ago
2007
ACM
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
113
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SAGA
2005
Springer
15 years 7 months ago
2005
Springer
We consider temporal aspects of self-replication and evolvability – in particular, the massively asynchronous parallel and distributed nature of living systems. Formal views of s...
117
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CHES
2006
Springer
15 years 5 months ago
2006
Springer
This paper presents a Path Swapping (PS) method which enables to enhance the security of Quasi Delay Insensitive Asynchronous Circuits against Power Analysis (PA) attack. This appr...