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» High-level power estimation with interconnect effects
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DAC
2006
ACM
15 years 11 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
ASPDAC
1999
ACM
149views Hardware» more  ASPDAC 1999»
15 years 2 months ago
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance
: In VLSI circuits with deep sub-micron, the parasitic capacitance from interconnect is a very important factor determining circuit performances such as power and time-delay. The B...
Jinsong Hou, Zeyi Wang, Xianlong Hong
85
Voted
JSAC
2007
79views more  JSAC 2007»
14 years 10 months ago
Fundamental Limits in MIMO Broadcast Channels
— This paper studies the fundamental limits of MIMO broadcast channels from a high level, determining the sum-rate capacity of the system as a function of system paramaters, such...
Babak Hassibi, Masoud Sharif
MICRO
2002
IEEE
171views Hardware» more  MICRO 2002»
15 years 3 months ago
Orion: a power-performance simulator for interconnection networks
With the prevalence of server blades and systems-ona-chip (SoCs), interconnection networks are becoming an important part of the microprocessor landscape. However, there is limite...
Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad...

Publication
78views
15 years 1 months ago
Chloroplast microsatellites: measures of genetic diversity and the effect of homoplasy
Chloroplast microsatellites have been widely used in population genetic studies of conifers in recent years. However, their haplotype configurations suggest that they could have hi...
Navascués, M. & Emerson, B. C.