1773 search results - page 119 / 355 » High-level power estimation |
114
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DAC
2012
ACM
13 years 3 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
111
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BMCBI
2010
15 years 29 days ago
2010
Background: In many microarray experiments, analysis is severely hindered by a major difficulty: the small number of samples for which expression data has been measured. When one ...
100
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VLSID
2006
IEEE
16 years 1 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
91
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BMCBI
2008
15 years 29 days ago
2008
Background: Association testing is a powerful tool for identifying disease susceptibility genes underlying complex diseases. Technological advances have yielded a dramatic increas...
105
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GLVLSI
2007
IEEE
15 years 2 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...