1773 search results - page 120 / 355 » High-level power estimation |
94
Voted
ICCAD
2007
IEEE
15 years 9 months ago
2007
IEEE
— The need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. Embedded and highperformance mic...
93
Voted
ISLPED
2003
ACM
15 years 6 months ago
2003
ACM
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architec...
97
Voted
HICSS
2008
IEEE
15 years 7 months ago
2008
IEEE
1 This paper discusses measurements of the dynamic performance of electric power Phasor Measurement Units, PMUs, and their relation to the requirements of the IEEE Synchrophasor St...
ICASSP
2011
IEEE
14 years 4 months ago
2011
IEEE
Considering a two-way amplify-and-forward (AF) relay network and aiming to simultaneously maximize the two users’ mutual information lower bounds in the presence of channel esti...
DAC
1999
ACM
16 years 1 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...