Sciweavers

1773 search results - page 128 / 355
» High-level power estimation
Sort
View
98
Voted
TWC
2008
131views more  TWC 2008»
15 years 21 days ago
On channel estimation and optimal training design for amplify and forward relay networks
In this paper, we provide a complete study on the training based channel estimation issues for relay networks that employ the amplify-and-forward (AF) transmission scheme. We first...
Feifei Gao, Tao Cui, Arumugam Nallanathan
90
Voted
VLSID
2007
IEEE
142views VLSI» more  VLSID 2007»
16 years 1 months ago
Controllability-driven Power Virus Generation for Digital Circuits
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekanan...
ICCD
2006
IEEE
312views Hardware» more  ICCD 2006»
15 years 9 months ago
A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
Kimiyoshi Usami, Naoaki Ohkubo
DAC
1999
ACM
15 years 5 months ago
Automated Phase Assignment for the Synthesis of Low Power Domino Circuits
High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs. The problem is that domino logic comes at a...
Priyadarshan Patra, Unni Narayanan
113
Voted
CODES
2008
IEEE
15 years 29 days ago
Methodology for multi-granularity embedded processor power model generation for an ESL design flow
With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...
Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi,...