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» High-level power estimation
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118
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DATE
2004
IEEE
116views Hardware» more  DATE 2004»
15 years 4 months ago
Full-Chip Multilevel Routing for Power and Signal Integrity
Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-...
Jinjun Xiong, Lei He
83
Voted
FAST
2003
15 years 2 months ago
Modeling Hard-Disk Power Consumption
Excessive power consumption is a major barrier to the market acceptance of hard disks in mobile electronic devices. Studying and reducing power consumption, however, often involve...
John Zedlewski, Sumeet Sobti, Nitin Garg, Fengzhou...
99
Voted
ICCD
2008
IEEE
111views Hardware» more  ICCD 2008»
15 years 9 months ago
Power switch characterization for fine-grained dynamic voltage scaling
—Dynamic voltage scaling (DVS) provides power savings for systems with varying performance requirements. One low overhead implementation of DVS uses PMOS power switches to connec...
Liang Di, Mateja Putic, John Lach, Benton H. Calho...
USENIX
2003
15 years 2 months ago
Design and Implementation of Power-Aware Virtual Memory
Despite constant improvements in fabrication technology, hardware components are consuming more power than ever. With the everincreasing demand for higher performance in highly-in...
Hai Huang, Padmanabhan Pillai, Kang G. Shin
ICS
2010
Tsinghua U.
14 years 11 months ago
Decomposable and responsive power models for multicore processors using performance counters
Abstract—Power modeling based on performance monitoring counters (PMCs) has attracted the interest of many researchers since it become a quick approach to understand and analyse ...
Ramon Bertran, Marc González, Xavier Martor...