Sciweavers

1773 search results - page 1 / 355
» High-level power estimation
Sort
View
DAC
1997
ACM
13 years 10 months ago
Power Macromodeling for High Level Power Estimation
A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input output signal switching activity. The resulting...
Subodh Gupta, Farid N. Najm
ASPDAC
2007
ACM
110views Hardware» more  ASPDAC 2007»
13 years 10 months ago
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs
Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang
ICCAD
2003
IEEE
190views Hardware» more  ICCAD 2003»
14 years 3 months ago
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
—While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementat...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...
IPPS
2006
IEEE
14 years 8 days ago
A high level SoC power estimation based on IP modeling
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
David Elléouet, Nathalie Julien, Dominique ...
DATE
2000
IEEE
112views Hardware» more  DATE 2000»
13 years 10 months ago
A Discrete-Time Battery Model for High-Level Power Estimation
In this paper, we introduce a discrete-time model for the complete power supply sub-system that closely approximates the behavior of its circuit-level (i.e., HSpice), continuous-t...
Luca Benini, Giuliano Castelli, Alberto Macii, Enr...