38 search results - page 5 / 8 » High-level test synthesis for delay fault testability |
ICCAD
2006
IEEE
15 years 8 months ago
2006
IEEE
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target pat...
ASPDAC
2005
ACM
15 years 1 months ago
2005
ACM
Recent research results have shown that the traditional structural testing for delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults t...
DAC
2004
ACM
15 years 5 months ago
2004
ACM
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feed...
ICCAD
2003
IEEE
15 years 8 months ago
2003
IEEE
Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay...
ATS
1996
IEEE
15 years 3 months ago
1996
IEEE
In this paper, we present a novel and efticient approach to test MCM at the module as well as chip levels. Our design incorporates the concept of the multifrequency test method an...