38 search results - page 6 / 8 » High-level test synthesis for delay fault testability |
ITC
2000
IEEE
15 years 4 months ago
2000
IEEE
104
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DATE
1999
IEEE
15 years 4 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
ITC
1997
IEEE
15 years 3 months ago
1997
IEEE
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
105
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DATE
1997
IEEE
15 years 3 months ago
1997
IEEE
Many Built-In Self Test pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs o...
VTS
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...