537 search results - page 29 / 108 » High-precision interconnect analysis |
132
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CF
2007
ACM
15 years 5 months ago
2007
ACM
As we enter the era of petascale computing, system architects must plan for machines composed of tens or even hundreds of thousands of processors. Although fully connected network...
ISQED
2006
IEEE
15 years 7 months ago
2006
IEEE
— In this paper, we propose an efficient model order reduction (MOR) algorithm, called MTermMOR, for modeling interconnect circuits with large number of external ports. The prop...
103
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ICS
2003
Tsinghua U.
15 years 7 months ago
2003
Tsinghua U.
Power consumption is a critical issue in interconnection network design, driven by power-related design constraints, such as thermal and power delivery design. Usually, off-line w...
115
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ISCA
2008
IEEE
15 years 8 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
111
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ISCAPDCS
2004
15 years 3 months ago
2004
This paper shows that a novel network called the fat-stack is universally efficient when adequate capacity distribution is provided and is suitable for use as an interconnection n...