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IOLTS
2003
IEEE
133views Hardware» more  IOLTS 2003»
15 years 7 months ago
Power Consumption of Fault Tolerant Codes: the Active Elements
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...
Daniele Rossi, Steven V. E. S. van Dijk, Richard P...
SPAA
2003
ACM
15 years 7 months ago
Throughput-centric routing algorithm design
The increasing application space of interconnection networks now encompasses several applications, such as packet routing and I/O interconnect, where the throughput of a routing a...
Brian Towles, William J. Dally, Stephen P. Boyd
IPPS
1996
IEEE
15 years 6 months ago
Benefits of Processor Clustering in Designing Large Parallel Systems: When and How?
Advances in multiprocessor interconnect technologyare leading to high performance networks. However, software overheadsassociated with message passing are limiting the processors ...
Debashis Basak, Dhabaleswar K. Panda, Mohammad Ban...
NIPS
2000
15 years 3 months ago
The Missing Link - A Probabilistic Model of Document Content and Hypertext Connectivity
We describe a joint probabilistic model for modeling the contents and inter-connectivity of document collections such as sets of web pages or research paper archives. The model is...
David A. Cohn, Thomas Hofmann
ICCAD
1998
IEEE
98views Hardware» more  ICCAD 1998»
15 years 6 months ago
Determination of worst-case aggressor alignment for delay calculation
Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic...
Paul D. Gross, Ravishankar Arunachalam, Karthik Ra...