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VLSI
2007
Springer
15 years 8 months ago
Parametric structure-preserving model order reduction
Abstract—Analysis and verification environments for nextgeneration nano-scale RFIC designs must be able to cope with increasing design complexity and to account for new effects,...
Jorge Fernandez Villena, Wil H. A. Schilders, L. M...
ASPLOS
2006
ACM
15 years 7 months ago
Stealth prefetching
Prefetching in shared-memory multiprocessor systems is an increasingly difficult problem. As system designs grow to incorporate larger numbers of faster processors, memory latency...
Jason F. Cantin, Mikko H. Lipasti, James E. Smith
DATE
2005
IEEE
147views Hardware» more  DATE 2005»
15 years 7 months ago
Buffer Insertion Considering Process Variation
A comprehensive probabilistic methodology is proposed to solve the buffer insertion problem with the consideration of process variations. In contrast to a recent work, we point o...
Jinjun Xiong, King Ho Tam, Lei He
ISVLSI
2003
IEEE
91views VLSI» more  ISVLSI 2003»
15 years 7 months ago
Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools
Three-dimensional integration technologies have been proposed in order to mitigate design challenges posed by deep-submicron interconnect. By providing multiple layers of active d...
Shamik Das, Anantha Chandrakasan, Rafael Reif
104
Voted
DATE
2002
IEEE
154views Hardware» more  DATE 2002»
15 years 6 months ago
Low Power Error Resilient Encoding for On-Chip Data Buses
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
Davide Bertozzi, Luca Benini, Giovanni De Micheli