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DAC
2006
ACM
16 years 2 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...
ICS
2007
Tsinghua U.
15 years 8 months ago
Optimization and bottleneck analysis of network block I/O in commodity storage systems
Building commodity networked storage systems is an important architectural trend; Commodity servers hosting a moderate number of consumer-grade disks and interconnected with a hig...
Manolis Marazakis, Vassilis Papaefstathiou, Angelo...
HIPEAC
2005
Springer
15 years 7 months ago
Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture
Abstract. Designers of large parallel computers and clusters are becoming increasingly concerned with the cost and power consumption of the interconnection network. A simple way to...
Pedro Javier García, Jose Flich, José...
CORR
2008
Springer
150views Education» more  CORR 2008»
15 years 1 months ago
A Local Mean Field Analysis of Security Investments in Networks
Getting agents in the Internet, and in networks in general, to invest in and deploy security features and protocols is a challenge, in particular because of economic reasons arisi...
Marc Lelarge, Jean Bolot
MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
15 years 8 months ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...