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ICCAD
2004
IEEE
145views Hardware» more  ICCAD 2004»
15 years 10 months ago
Accurate estimation of global buffer delay within a floorplan
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar,...
ICCAD
2004
IEEE
95views Hardware» more  ICCAD 2004»
15 years 10 months ago
Low-power programmable routing circuitry for FPGAs
We propose two new FPGA routing switch designs that are programmable to operate in three different modes: highspeed, low-power or sleep. High-speed mode provides similar power an...
Jason Helge Anderson, Farid N. Najm
3DIC
2009
IEEE
279views Hardware» more  3DIC 2009»
15 years 8 months ago
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...
3DIC
2009
IEEE
153views Hardware» more  3DIC 2009»
15 years 8 months ago
Junction-level thermal extraction and simulation of 3DICs
Abstract—In 3DICs heat dissipating devices are stacked directly on top of each other leading to a higher heat density than in a comparable 2D chip. 3D integration also moves the ...
Samson Melamed, Thorlindur Thorolfsson, Adi Sriniv...
CCS
2009
ACM
15 years 8 months ago
On cellular botnets: measuring the impact of malicious devices on a cellular network core
The vast expansion of interconnectivity with the Internet and the rapid evolution of highly-capable but largely insecure mobile devices threatens cellular networks. In this paper,...
Patrick Traynor, Michael Lin, Machigar Ongtang, Vi...