537 search results - page 8 / 108 » High-precision interconnect analysis |
78
Voted
DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
—Recent developments have shown the possibility of leveraging silicon nanophotonic technologies for chip-scale interconnection fabrics that deliver high bandwidth and power effi...
91
Voted
DATE
2005
IEEE
15 years 1 months ago
2005
IEEE
This paper reports a novel simulation methodology for analysis and prediction of substrate noise impact on analog / RF circuits taking into account the role of the parasitic resis...
119
click to vote
PE
2006
Springer
14 years 11 months ago
2006
Springer
In a multi-level cache such as those used for web caching, a hit at level l leads to the caching of the requested object in all intermediate caches on the reverse path (levels l -...
83
Voted
ISQED
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper presents a two-step, RC-interconnect insensitive linear time-varying (LTV) driver model for gate-level timing calculation. We show how to characterize a driver with the...
99
Voted
DAC
2000
ACM
16 years 19 days ago
2000
ACM
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that...