24 search results - page 2 / 5 » High-speed VLSI architecture for parallel Reed-Solomon decod... |
104
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CODES
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
SIGCOMM
1990
ACM
15 years 1 months ago
1990
ACM
Traditionally, a transport protocol corrects errors in a computer communication network using a simple ARQ protocol. With the arrival of broadband networks, forward error correcti...
ISVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
The authors present a turbo soft-in soft-out (SISO) decoder based on Max-Log maximum a posteriori (ML-MAP) algorithm implemented with sliding window (SW) method. A novel technique...
105
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TSP
2008
14 years 9 months ago
2008
This paper presents a systematic high-speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D D...
ARVLSI
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...