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SIGSOFT
2005
ACM
16 years 5 months ago
Fluent temporal logic for discrete-time event-based models
Fluent model checking is an automated technique for verifying that an event-based operational model satisfies some state-based declarative properties. The link between the event-b...
Emmanuel Letier, Jeff Kramer, Jeff Magee, Sebasti&...
PATMOS
2007
Springer
15 years 11 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
EH
2003
IEEE
247views Hardware» more  EH 2003»
15 years 10 months ago
Evolvable Building Blocks for Analog Fuzzy Logic Controllers
This work discusses the use of an Evolvable Hardware (EHW) platform in the synthesis of analog electronic circuits for Fuzzy Logic Controllers. A Fuzzy Logic Controller (FLC) is d...
Jorge Luís Machado do Amaral, José F...
KDD
2009
ACM
175views Data Mining» more  KDD 2009»
15 years 9 months ago
Multi-class protein fold recognition using large margin logic based divide and conquer learning
Inductive Logic Programming (ILP) systems have been successfully applied to solve complex problems in bioinformatics by viewing them as binary classification tasks. It remains an...
Huma Lodhi, Stephen Muggleton, Michael J. E. Stern...
ATS
2005
IEEE
164views Hardware» more  ATS 2005»
15 years 6 months ago
A Family of Logical Fault Models for Reversible Circuits
Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional ...
Ilia Polian, Thomas Fiehn, Bernd Becker, John P. H...