Sciweavers

851 search results - page 132 / 171
» History Effects and Verification
Sort
View
ICCAD
2000
IEEE
88views Hardware» more  ICCAD 2000»
15 years 4 months ago
Hierarchical Interconnect Circuit Models
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pi...
ICCAD
1994
IEEE
122views Hardware» more  ICCAD 1994»
15 years 4 months ago
An enhanced flow model for constraint handling in hierarchical multi-view design environments
In this paper we present an enhanced design flow model that increases the capabilities of a CAD framework to support design activities on hierarchical multi-view design descriptio...
Pieter van der Wolf, K. Olav ten Bosch, Alfred van...
ASPDAC
2007
ACM
144views Hardware» more  ASPDAC 2007»
15 years 3 months ago
Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method
With semiconductor fabrication technologies scaled below 100 nm, the design-manufacturing interface becomes more and more complicated. The resultant process variability causes a nu...
Alexander V. Mitev, Michael Marefat, Dongsheng Ma,...
ECAI
2006
Springer
15 years 3 months ago
Compact Representation of Sets of Binary Constraints
Abstract. We address the problem of representing big sets of binary constraints compactly. Binary constraints in the form of 2literal clauses are ubiquitous in propositional formul...
Jussi Rintanen
ESOP
2006
Springer
15 years 3 months ago
A Typed Assembly Language for Confidentiality
Language-based information-flow analysis is promising in protecting data confidentiality. Although much work has been carried out in this area, relatively little has been done for ...
Dachuan Yu, Nayeem Islam