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DAC
2004
ACM
16 years 22 days ago
Efficient equivalence checking with partitions and hierarchical cut-points
Previous results show that both flat and hierarchical methodologies present obstacles to effectively completing combinational equivalence checking. A new approach that combines th...
Demos Anastasakis, Lisa McIlwain, Slawomir Pilarsk...
ICPR
2008
IEEE
16 years 29 days ago
Towards mobile authentication using dynamic signature verification: Useful features and performance evaluation
The proliferation of handheld devices such as PDAs and smartphones represents a new scenario for automatic signature verification. Traditionally, research on signature verificatio...
Marcos Martinez-Diaz, Julian Fiérrez-Aguila...
ISCAS
2003
IEEE
89views Hardware» more  ISCAS 2003»
15 years 5 months ago
Synthesizing checkers for on-line verification of System-on-Chip designs
In modern System-on-Chip (SoC) designs verification becomes the major bottleneck. Since by using state-of-theart techniques complete designs cannot be fully formally verified, it ...
Rolf Drechsler
FMCAD
2000
Springer
15 years 3 months ago
A Methodology for Large-Scale Hardware Verification
Abstract. We present a formal verification methodology for datapathdominated hardware. This provides a systematic but flexible framework within which to organize the activities und...
Mark Aagaard, Robert B. Jones, Thomas F. Melham, J...
FGR
2008
IEEE
176views Biometrics» more  FGR 2008»
14 years 12 months ago
Non-linear fusion of local matching scores for face verification
This paper presents a face verification framework for fusing matching scores that measure similarities of local facial features. The framework is aimed to handle an openset verifi...
Ziheng Zhou, Samuel Chindaro, Farzin Deravi