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VLSID
2002
IEEE
83views VLSI» more  VLSID 2002»
16 years 6 days ago
Identifying Redundant Wire Replacements for Synthesis and Verification
We propose the redundancy identification of wire replacement faults. The solutions rely on the satisfiability (SAT) formulation of redundancy identification, augmented with the me...
Katarzyna Radecka, Zeljko Zilic
ICIC
2005
Springer
15 years 5 months ago
Signature Verification Using Wavelet Transform and Support Vector Machine
In this paper, we propose a novel on-line handwritten signature verification method. Firstly, the pen-position parameters of the on-line signature are decomposed into multiscale si...
Hong-Wei Ji, Zhong-Hua Quan
UML
2004
Springer
15 years 5 months ago
System-on-Chip Verification Process Using UML
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro...
DBPL
1997
Springer
133views Database» more  DBPL 1997»
15 years 4 months ago
Automatic Verification of Transactions on an Object-Oriented Database
Abstract. In the context of the object-oriented data model, a compiletime approach is given that provides for a significant reduction of the amount of run-time transaction overhead...
David Spelt, Herman Balsters
JLP
2008
75views more  JLP 2008»
14 years 11 months ago
Automated verification of selected equivalences for security protocols
In the analysis of security protocols, methods and tools for reasoning about protocol behaviors have been quite effective. We aim to expand the scope of those methods and tools. W...
Bruno Blanchet, Martín Abadi, Cédric...