This paper outlines a formal model of the Intel IA-64 architecture, and explains how this model can be used to verify the correctness of assembly-level code optimizations. The form...
Many code analysis techniques for optimization, debugging, or parallelization need to perform runtime disambiguation of sets of addresses. Such operations can be supported efficie...
James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas
Wireless sensor network (WSN) applications sense events in-situ and compute results in-network. Their software components should run on platforms with stringent constraints on nod...
Cyclic genetic algorithms can be used to generate single loop control programs for robots. While successful in generating controllers for individual leg movement, gait generation,...
Abstract--This paper addresses the problem of adaptively allocating the bits and the power among a set of parallel subchannels. A frame-oriented transmission with convolutional cod...