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TPHOL
2000
IEEE
15 years 4 months ago
Verified Optimizations for the Intel IA-64 Architecture
This paper outlines a formal model of the Intel IA-64 architecture, and explains how this model can be used to verify the correctness of assembly-level code optimizations. The form...
Jim Grundy
87
Voted
ASPLOS
2008
ACM
15 years 2 months ago
SoftSig: software-exposed hardware signatures for code analysis and optimization
Many code analysis techniques for optimization, debugging, or parallelization need to perform runtime disambiguation of sets of addresses. Such operations can be supported efficie...
James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas
105
Voted
QSIC
2007
IEEE
15 years 7 months ago
Synthesizing Component-Based WSN Applications via Automatic Combination of Code Optimization Techniques
Wireless sensor network (WSN) applications sense events in-situ and compute results in-network. Their software components should run on platforms with stringent constraints on nod...
Zhenyu Zhang, W. K. Chan, T. H. Tse
GECCO
2005
Springer
175views Optimization» more  GECCO 2005»
15 years 6 months ago
Evolution of multi-loop controllers for fixed morphology with a cyclic genetic algorithm
Cyclic genetic algorithms can be used to generate single loop control programs for robots. While successful in generating controllers for individual leg movement, gait generation,...
Gary B. Parker, Ramona Georgescu
111
Voted
TSP
2008
83views more  TSP 2008»
15 years 21 days ago
Bit and Power Allocation for Goodput Optimization in Coded Parallel Subchannels With ARQ
Abstract--This paper addresses the problem of adaptively allocating the bits and the power among a set of parallel subchannels. A frame-oriented transmission with convolutional cod...
B. Devillers, Jérôme Louveaux, Luc Va...