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DAC
2012
ACM
13 years 2 months ago
A metric for layout-friendly microarchitecture optimization in high-level synthesis
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
Jason Cong, Bin Liu
ICSE
2001
IEEE-ACM
15 years 4 months ago
A Scenario-Driven Approach to Traceability
Design traceability has been widely recognized as being an integral aspect of software development. In the past years this fact has been amplified due to the increased use of lega...
Alexander Egyed
APN
2001
Springer
15 years 4 months ago
Rewriting Logic as a Unifying Framework for Petri Nets
We propose rewriting logic as a unifying framework for a wide range of Petri nets models. We treat in detail place/transition nets and important extensions of the basic model by in...
Mark-Oliver Stehr, José Meseguer, Peter Csa...
PAMI
2006
186views more  PAMI 2006»
14 years 11 months ago
Performance Evaluation of Fingerprint Verification Systems
This paper is concerned with the performance evaluation of fingerprint verification systems. After an initial classification of biometric testing initiatives, we explore both the t...
Raffaele Cappelli, Dario Maio, Davide Maltoni, Jam...
IPPS
1999
IEEE
15 years 4 months ago
Non-Preemptive Scheduling of Real-Time Threads on Multi-Level-Context Architectures
The rapid progress in high-performance microprocessor design has made it di cult to adapt real-time scheduling results to new models of microprocessor hardware, thus leaving an un...
Jan Jonsson, Henrik Lönn, Kang G. Shin