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TVLSI
2010
14 years 7 months ago
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
Rupak Samanta, Jiang Hu, Peng Li
186
Voted
ICONFERENCE
2012
13 years 8 months ago
No forests without trees: particulars and patterns in visualizing personal communication
When people use visualizations of conversational archives, they typically reflect on particular events, rather than patterns of activity over time. We explore whether this is a fu...
Ou Jie Zhao, Tiffany Ng, Dan Cosley
79
Voted
DFT
2005
IEEE
90views VLSI» more  DFT 2005»
15 years 6 months ago
On the Modeling and Analysis of Jitter in ATE Using Matlab
This paper presents a new jitter component analysis method for mixed mode VLSI chip testing in Automatic Test Equipment (ATE). The separate components are analyzed individually an...
Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio L...
111
Voted
SODA
1998
ACM
157views Algorithms» more  SODA 1998»
15 years 1 months ago
A Polynomial Time Approximation Scheme for Minimum Routing Cost Spanning Trees
Given an undirected graph with nonnegative costs on the edges, the routing cost of any of its spanning trees is the sum over all pairs of vertices of the cost of the path between t...
Bang Ye Wu, Giuseppe Lancia, Vineet Bafna, Kun-Mao...
AI
2010
Springer
15 years 17 days ago
Understanding the scalability of Bayesian network inference using clique tree growth curves
Bayesian networks (BNs) are used to represent and ef ciently compute with multi-variate probability distributions in a wide range of disciplines. One of the main approaches to per...
Ole J. Mengshoel