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DAC
2000
ACM
15 years 11 months ago
METRICS: a system architecture for design process optimization
We describe METRICS, a system to recover design productivity via new infrastructure for design process optimization. METRICS seeks to treat system design and implementation as a s...
Stephen Fenstermaker, David George, Andrew B. Kahn...
DAC
2004
ACM
15 years 11 months ago
Exploiting structure in symmetry detection for CNF
Instances of the Boolean satisfiability problem (SAT) arise in many areas of circuit design and verification. These instances are typically constructed from some human-designed ar...
Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah...
VLSID
2007
IEEE
153views VLSI» more  VLSID 2007»
15 years 10 months ago
Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions
Boolean Satisfiability is seeing increasing use as a decision procedure in Electronic Design Automation (EDA) and other domains. Most applications encode their domain specific cons...
Zhaohui Fu, Sharad Malik
ISQED
2010
IEEE
120views Hardware» more  ISQED 2010»
15 years 4 months ago
Methodology from chaos in IC implementation
— Algorithms and tools used for IC implementation do not show deterministic and predictable behaviors with input parameter changes. Due to suboptimality and inaccuracy of underly...
Kwangok Jeong, Andrew B. Kahng
HOST
2008
IEEE
15 years 4 months ago
Circuit CAD Tools as a Security Threat
Abstract: Circuit CAD Tools as a Security Threat Jarrod A. Roy†, Farinaz Koushanfar‡ and Igor L. Markov† †The University of Michigan, Department of EECS, 2260 Hayward Ave.,...
Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov