Sciweavers

5314 search results - page 913 / 1063
» Hybrid Dynamic Programming
Sort
View
DATE
2003
IEEE
132views Hardware» more  DATE 2003»
15 years 3 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
15 years 3 months ago
A Novel Metric for Interconnect Architecture Performance
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Mud...
ICDAR
2003
IEEE
15 years 3 months ago
A Study on Top-down Word Image Generation for Handwritten Word Recognition
This paper describes a top-down word image generation model for holistic handwritten word recognition. To generate a word image, it uses likelihoods based, respectively, on a ling...
Eiki Ishidera, Daisuke Nishiwaki
ICPP
2003
IEEE
15 years 3 months ago
Enabling Partial Cache Line Prefetching Through Data Compression
Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buff...
Youtao Zhang, Rajiv Gupta
ICPP
2003
IEEE
15 years 3 months ago
Procedural Level Address Offset Assignment of DSP Applications with Loops
Automatic optimization of address offset assignment for DSP applications, which reduces the number of address arithmetic instructions to meet the tight memory size restrictions an...
Youtao Zhang, Jun Yang 0002