17288 search results - page 3250 / 3458 » Hybrid Optimizations: Which Optimization Algorithm to Use |
153
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PDP
2010
IEEE
15 years 8 months ago
2010
IEEE
The increasing numbers of cores, shared caches and memory nodes within machines introduces a complex hardware topology. High-performance computing applications now have to carefull...
145
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HPCA
1999
IEEE
15 years 8 months ago
1999
IEEE
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
135
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ICCAD
1999
IEEE
15 years 8 months ago
1999
IEEE
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
130
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MSS
1999
IEEE
15 years 8 months ago
1999
IEEE
When the BaBar experiment at the Stanford Linear Accelerator Center starts in April 1999, it will generate approximately 200TB/year of data at a rate of 10MB/sec for 10 years. A m...
138
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ICS
1999
Tsinghua U.
15 years 8 months ago
1999
Tsinghua U.
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...