121 search results - page 15 / 25 » Hybrid cache architecture with disparate memory technologies |
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
121
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
100
Voted
IEEEPACT
2002
IEEE
15 years 2 months ago
2002
IEEE
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with L...
IPPS
2010
IEEE
14 years 7 months ago
2010
IEEE
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
RTAS
2005
IEEE
15 years 3 months ago
2005
IEEE
Dynamic voltage and frequency scaling is increasingly being used to reduce the energy requirements of embedded and real-time applications by exploiting idle CPU resources, while s...