121 search results - page 4 / 25 » Hybrid cache architecture with disparate memory technologies |
HIPEAC
2010
Springer
13 years 8 months ago
2010
Springer
Abstract. Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include...
DAC
2009
ACM
14 years 1 months ago
2009
ACM
In this paper, we propose PDRAM, a novel energy efficient main memory architecture based on phase change random access memory (PRAM) and DRAM. The paper explores the challenges i...
PCI
2005
Springer
13 years 12 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
DAC
2009
ACM
14 years 7 months ago
2009
ACM
In this paper, we propose PDRAM, a novel energy efficient main memory architecture based on phase change random access memory (PRAM) and DRAM. The paper explores the challenges in...
ISCA
2009
IEEE
14 years 1 months ago
2009
IEEE
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...