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JUCS
2000
120views more  JUCS 2000»
14 years 11 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
JACM
2010
137views more  JACM 2010»
14 years 10 months ago
Reconciling description logics and rules
Description logics (DLs) and rules are formalisms that emphasize different aspects of knowledge representation: whereas DLs are focused on specifying and reasoning about conceptual...
Boris Motik, Riccardo Rosati
VTC
2010
IEEE
136views Communications» more  VTC 2010»
14 years 10 months ago
HARQ Aided Systematic LT Coding for Amplify-Forward and Decode-Forward Cooperation
—Systematic Luby Transform (SLT) codes constitute rateless codes, which are capable of adaptively adjusting their code rate depending on the channel quality without explicit chan...
Hoang Anh Ngo, Thanh Dang Nguyen, Lajos Hanzo
IPPS
2010
IEEE
14 years 9 months ago
Oversubscription on multicore processors
Abstract: Existing multicore systems already provide deep levels of thread parallelism. Hybrid programming models and composability of parallel libraries are very active areas of r...
Costin Iancu, Steven Hofmeyr, Filip Blagojevic, Yi...
BMCBI
2010
121views more  BMCBI 2010»
14 years 9 months ago
Computing DNA duplex instability profiles efficiently with a two-state model: trends of promoters and binding sites
Background: DNA instability profiles have been used recently for predicting the transcriptional start site and the location of core promoters, and to gain insight into promoter ac...
Miriam R. Kantorovitz, Zoi Rapti, Vladimir Gelev, ...