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LCTRTS
2000
Springer
15 years 1 months ago
Reordering Memory Bus Transactions for Reduced Power Consumption
Low energy consumption is becoming the primary design consideration for battery-operated and portable embedded systems, such as personal digital assistants, digital still and movi...
Bruce R. Childers, Tarun Nakra
ASPLOS
1992
ACM
15 years 2 months ago
Closing the Window of Vulnerability in Multiphase Memory Transactions
Multiprocessor architects have begun to explore several mechanisms such as prefetching, context-switching and software-assisted dynamic cache-coherence, which transform single-pha...
John Kubiatowicz, David Chaiken, Anant Agarwal
PVLDB
2008
96views more  PVLDB 2008»
14 years 9 months ago
H-store: a high-performance, distributed main memory transaction processing system
Our previous work has shown that architectural and application shifts have resulted in modern OLTP databases increasingly falling short of optimal performance [10]. In particular,...
Robert Kallman, Hideaki Kimura, Jonathan Natkins, ...
PPOPP
2009
ACM
15 years 2 months ago
Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions
Boosted transactions offer an attractive method that enables programmers to create larger transactions that scale well and offer deadlock-free guarantees. However, as boosted tran...
Chinmay Eishan Kulkarni, Osman S. Unsal, Adri&aacu...
FCCM
2007
IEEE
124views VLSI» more  FCCM 2007»
15 years 4 months ago
A Hybrid Memory Sub-system for Video Coding Applications
This paper introduces a parameterisable, application and platform-independent, hybrid memory sub-system for custom hardware. This memory sub-system consists of a scratchpad memory...
Su-Shin Ang, George A. Constantinides, Wayne Luk, ...