Sciweavers

119 search results - page 16 / 24
» Hyperreconfigurable Architectures for Fast Run Time Reconfig...
Sort
View
IFIP
1998
Springer
15 years 1 months ago
Combining Static Partitioning with Dynamic Distribution of Threads
This paper presents a hybrid approach to automatic parallelization of computer programs which combines static extraction of threads (tasks) with dynamic scheduling for parallel an...
Ronald Moore, Melanie Klang, Bernd Klauer, Klaus W...
71
Voted
CF
2007
ACM
15 years 1 months ago
Fast compiler optimisation evaluation using code-feature based performance prediction
Performance tuning is an important and time consuming task which may have to be repeated for each new application and platform. Although iterative optimisation can automate this p...
Christophe Dubach, John Cavazos, Björn Franke...
152
Voted
VLSISP
2011
358views Database» more  VLSISP 2011»
14 years 4 months ago
Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition
Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from superlinear increases in ...
Karthik Nagarajan, Brian Holland, Alan D. George, ...
RECONFIG
2008
IEEE
268views VLSI» more  RECONFIG 2008»
15 years 3 months ago
Parametric, Secure and Compact Implementation of RSA on FPGA
1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...
Ersin Oksuzoglu, Erkay Savas
ASAP
2008
IEEE
120views Hardware» more  ASAP 2008»
14 years 11 months ago
Lightweight DMA management mechanisms for multiprocessors on FPGA
This paper presents a multiprocessor system on FPGA that adopts Direct Memory Access (DMA) mechanisms to move data between the external memory and the local memory of each process...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...