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3DIC
2009
IEEE
263views Hardware» more  3DIC 2009»
15 years 28 days ago
3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)
Abstract— Networks-on-chip (NoC) is emerging as a key onchip communication architecture for multiprocessor systemson-chip (MPSoC). In traditional electronic NoCs, high bandwidth ...
Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Mo Kwa...
HIPEAC
2005
Springer
15 years 3 months ago
Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems
Abstract. Power efficiency has become a key design trade-off in embedded system designs. For system-on-a-chip embedded systems, an external bus interconnects embedded processor co...
Ke Ning, David R. Kaeli
ISLPED
2006
ACM
145views Hardware» more  ISLPED 2006»
15 years 3 months ago
An optimal analytical solution for processor speed control with thermal constraints
As semiconductor manufacturing technology scales to smaller device sizes, the power consumption of clocked digital ICs begins to increase. Dynamic voltage and frequency scaling (D...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...
82
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TPDS
2008
126views more  TPDS 2008»
14 years 9 months ago
Efficient Directional Network Backbone Construction in Mobile Ad Hoc Networks
In this paper, we consider the issue of constructing an energy-efficient virtual network backbone in mobile ad hoc networks (MANETs) for broadcasting applications using directiona...
Shuhui Yang, Jie Wu, Fei Dai
TVLSI
2010
14 years 4 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...