128 search results - page 10 / 26 » ILP-based optimization of sequential circuits for low power |
67
Voted
ISLPED
1997
ACM
15 years 1 months ago
1997
ACM
In this paper we report the fully depleted CMOS/SOI device design guidelines for low power applications. Optimal technology, device and circuit parameters are discussed and compar...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
DAC
1999
ACM
15 years 10 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
ASPDAC
2009
ACM
15 years 2 months ago
2009
ACM
Iterative retiming and resynthesis is a powerful way to optimize sequential circuits but its massive adoption has been hampered by the hardness of verification. This paper tackle...