128 search results - page 20 / 26 » ILP-based optimization of sequential circuits for low power |
ISLPED
2003
ACM
15 years 2 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
ICCAD
2007
IEEE
15 years 6 months ago
2007
IEEE
Among the post-CMOS technologies currently under investigation, quantum computing (QC) holds a special place. QC offers not only extremely small size and low power, but also expon...
57
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ISLPED
2003
ACM
15 years 2 months ago
2003
ACM
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) im...
ICCD
1996
IEEE
15 years 1 months ago
1996
IEEE
For circuits where there may be latches with no reset line, we show how to replace some of them with combinational logic. All previous work in sequential optimization by latch rem...
104
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GLVLSI
2003
IEEE
15 years 2 months ago
2003
IEEE
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...