128 search results - page 6 / 26 » ILP-based optimization of sequential circuits for low power |
112
click to vote
DATE
2010
IEEE
14 years 10 months ago
2010
IEEE
—Starting from sequential programs, we present an approach combining data reuse, multi-level MapReduce, and pipelining to automatically find the most power-efficient designs th...
106
click to vote
TC
2008
14 years 11 months ago
2008
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during te...
ICCAD
2008
IEEE
15 years 6 months ago
2008
IEEE
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
94
Voted
ICCAD
1996
IEEE
15 years 3 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
76
Voted
ICCAD
1997
IEEE
15 years 3 months ago
1997
IEEE
An abundance of research e orts in low power logic synthesis have so far been focused on and or or nand nor based logic. A typical approach is to rst generate an initial multi-lev...