128 search results - page 9 / 26 » ILP-based optimization of sequential circuits for low power |
VLSID
2001
IEEE
15 years 9 months ago
2001
IEEE
Development of the process technology for dual threshold (dual Vth ) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance ...
DAC
1997
ACM
15 years 1 months ago
1997
ACM
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
ISVLSI
2002
IEEE
15 years 2 months ago
2002
IEEE
Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be re...
ISLPED
2004
ACM
15 years 2 months ago
2004
ACM
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
DAC
2008
ACM
15 years 10 months ago
2008
ACM
A low power passive equalizer using RL terminator is proposed and optimized in this work. The equalizer includes an inductor in series with the resistive terminator, which boosts ...