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DATE
2006
IEEE
100views Hardware» more  DATE 2006»
15 years 6 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
CODES
2003
IEEE
15 years 5 months ago
Security wrappers and power analysis for SoC technologies
Future wireless internet enabled devices will be increasingly powerful supporting many more applications including one of the most crucial, security. Although SoCs offer more resi...
Catherine H. Gebotys, Y. Zhang
SP
1997
IEEE
135views Security Privacy» more  SP 1997»
15 years 4 months ago
Analysis of a Denial of Service Attack on TCP
This paper analyzes a network-baseddenial of service attack for IP (Internet Protocol) based networks. It is popularly called SYN flooding. It works by an attacker sending many T...
Christoph L. Schuba, Ivan Krsul, Markus G. Kuhn, E...
SIGIR
2010
ACM
15 years 2 days ago
Analysis of structural relationships for hierarchical cluster labeling
Cluster label quality is crucial for browsing topic hierarchies obtained via document clustering. Intuitively, the hierarchical structure should influence the labeling accuracy. H...
Markus Muhr, Roman Kern, Michael Granitzer
80
Voted
ASPDAC
2010
ACM
112views Hardware» more  ASPDAC 2010»
14 years 10 months ago
Optimizing blocks in an SoC using symbolic code-statement reachability analysis
Abstract-- Optimizing blocks in a System-on-Chip (SoC) circuit is becoming more and more important nowadays due to the use of third-party Intellectual Properties (IPs) and reused d...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo