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» IP Reuse in the System on a Chip Era
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ISQED
2005
IEEE
116views Hardware» more  ISQED 2005»
15 years 3 months ago
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost
Today's System-on-a-Chip (SoC) design methodology provides an efficient way to develop highly integrated systems on a single chip by utilizing pre-designed intellectual prope...
Subhrajit Bhattacharya, John A. Darringer, Daniel ...
ISPD
2011
ACM
253views Hardware» more  ISPD 2011»
14 years 10 days ago
Assembling 2D blocks into 3D chips
Three-dimensional ICs promise to significantly extend the scale of system integration and facilitate new-generation electronics. However, progress in commercial 3D ICs has been s...
Johann Knechtel, Igor L. Markov, Jens Lienig
ISQED
2003
IEEE
215views Hardware» more  ISQED 2003»
15 years 2 months ago
Low-Cost and Real-Time Super-Resolution over a Video Encoder IP
This paper addresses a low-cost and real-time solution for the implementation of super-resolution (SR) algorithms over SOC (System-On-Chip) platforms in order to achieve high-qual...
Gustavo Marrero Callicó, Antonio Nú&...
ACSD
2004
IEEE
124views Hardware» more  ACSD 2004»
15 years 1 months ago
A Behavioral Type Inference System for Compositional System-on-Chip Design
The design productivity gap has been recognized by the semiconductor industry as one of the major threats to the continued growth of system-on-chips and embedded systems. Ad-hoc s...
Jean-Pierre Talpin, David Berner, Sandeep K. Shukl...
ICCAD
2000
IEEE
97views Hardware» more  ICCAD 2000»
15 years 1 months ago
Error Catch and Analysis for Semiconductor Memories Using March Tests
We present an error catch and analysis (ECA) system for semiconductor memories. The system consists of a test algorithm generator called TAGS, a fault simulator called RAMSES, and...
Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-L...