111 search results - page 13 / 23 » IPR: An Integrated Placement and Routing Algorithm |
FPGA
2003
ACM
15 years 4 months ago
2003
ACM
We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-D...
ISCA
2009
IEEE
15 years 6 months ago
2009
IEEE
In the near term, Moore’s law will continue to provide an increasing number of transistors and therefore an increasing number of on-chip cores. Limited pin bandwidth prevents th...
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ICCAD
2006
IEEE
15 years 8 months ago
2006
IEEE
The wire length estimation is the bottleneck of packing based block placers. To cope with this problem, we present a fast wire length estimation method in this paper. The key idea...
FPGA
2010
ACM
15 years 8 months ago
2010
ACM
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
ICCAD
2006
IEEE
15 years 8 months ago
2006
IEEE
The use of CMOS nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. Rising design comp...